1. Field of the Invention
The present invention relates to a method for manufacturing a wafer level chip scale package.
2. Description of the Related Art
Lately, the electronic industry has been seeking to manufacture electronic products that are extremely small, light weight, operate at high speeds, have multiple functions and have high performance, all at an effective cost. One of the methods used to try to attain such a goal is a package assembly technique. Thanks to this technique, new types of packages have been developed, for example, a chip scale or chip size package (CSP). The CSP has a number of advantages over typical plastic packages. Of all the advantages, the most important is the package size. According to international semiconductor associations, such as the Joint Electron Device Engineering Council (JEDEC), and Electronic Industry Association of Japan (EIAJ), the CSP is defined as a package whose size is not larger than 1.2 times the size of the chip.
The CSP has been mainly employed in electronic products requiring miniaturization and mobility, such as digital camcorders, portable telephones, notebooks, and memory cards. CSPs include semiconductor devices such as digital signal processors (DSP), application specific integrated circuits (ASIC), and micro controllers. CSPs also include memory devices such as dynamic random access memories (DRAM) and flash memories. Use of CSPs having memory devices is steadily increasing. Over fifty varieties of CSPs are at present being developed or produced all over the world.
The CSP has, however, some drawbacks. For example, there are some difficulties in obtaining acceptable reliability of the package. Further, the CSP needs additional equipment requiring large quantities of raw and/or subsidiary materials and high per unit costs of production, which causes a reduction in price competition.
In order to overcome these drawbacks, a wafer level chip scale package (WLCSP) has appeared as a solution.
Generally, a package is manufactured through wafer fabrication, cutting, and assembly processes. The package assembly process employs separate equipment and raw/subsidiary materials from those of the wafer fabrication process. The WLCSP, however, can allow manufacture of the packages as final products at wafer level, i.e. without dividing them into individual chips. The WLCSP can apply the equipment and processes used for the wafer fabrication process to complete the package assembly process as well. Therefore, the WLCSP may allow the manufacture of packages at a more effective cost.
FIG. 1 is a plan view of a conventional WLCSP 20. FIG. 2 is a cross-sectional view taken along the line 2—2 in FIG. 1. Solder balls (28 of FIG. 2) are not illustrated in FIG. 1 to illustrate a ball pad 23.
Referring to FIGS. 1 and 2, a CSP 20 comprises a semiconductor chip 14. The semiconductor chip 14 has a plurality of chip pads 11. The chip pads 11 are disposed at the periphery of an upper surface of a silicon substrate 12. A metal wiring layer 21 is formed for redistribution of the chip pad 11. The solder balls 28 are formed on ball pads 23 located at the ends of the metal wiring layer 21.
The semiconductor chip 14 comprises the chip pads 11 and a passivation layer 13. The chip pads 11 are electrically connected to an integrated circuit (IC) of the silicon substrate 12. The passivation layer 13 protects the IC and the chip pads 11. The chip pads 11 are made of Al and the passivation layer 13 is made of oxide film or nitride film.
A dielectric layer 22 (hereinafter referred to as a first dielectric layer) is formed on the passivation layer 13 at a predetermined thickness, and is used for formation of the metal wiring layer 21. The first dielectric layer 22 overlies the passivation layer 13, leaving a portion of each chip pad 11 exposed.
A metal base layer 25 is formed on the chip pad 11 and the first dielectric layer 22, in the position on which the metal wiring layer 21 is to be formed.
The metal wiring layer 21 is formed on the first dielectric layer 22 toward the center of the silicon substrate 12. The metal wiring layer 21 is connected to the chip pads 11. The ball pads 23 are formed at the ends of the metal wiring layer 21 for formation of the solder balls 28.
Another dielectric layer 24 (hereinafter referred to as a second dielectric layer) is formed to a predetermined thickness on the entire surface of the silicon substrate 12 except for the ball pads 23. The second dielectric layer 24 covers the passivation layer 13, the metal wiring layer 21, and the first dielectric layer 22.
After the solder ball 28 is placed on a ball pad 23, the solder ball 28 is fixed or connected to the ball pad 23 through a solder reflow process using heat.
The conventional CSP 20 has several disadvantages. For example, the size of the solder ball 28 is small and the ball pad 23 is exposed only through a connection hole 27 formed in the second dielectric layer 24. Thus, the contact area between the ball pad 23 and the solder ball 28 is relatively small. The narrower the pitch between two adjacent ball pads 23 is, the smaller the contact area between the ball pad 23 and the solder ball 28 must be. Therefore, the connection reliability of the solder ball 28 to the ball pad 23 is reduced together with the reduction of the pitch between the ball pads 23. In addition, the ball pad 23 is formed in a circular shape and is enclosed by the second dielectric layer 24. Thus, even though the solder ball 28 is not metallically connected with the second dielectric layer 24, it is in contact with it. This plus the fact that the connection of the solder ball 28 is made only to the flat surface of the ball pad 23 may reduce the connection reliability of the solder ball 28 to the ball pad 23.